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1 pcs ESP-WROOM-32 WiFi + Bluetooth 4.2 dual-core CPU MCU low-power Bluetooth 240MHZ ESP32 chip ESP-32S

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ESP32 is a WiFi and Bluetooth system-on-chip (SoC) with industry-leading RF performance, low power and high integration advantages. The ESP32 integrates complete transmit / receive RF functions including antenna switches, RF balun, power amplifiers, low noise amplifiers, filters, power management modules and advanced self-calibration circuitry. The self-calibration circuit implements dynamic auto-tuning to eliminate defects in external circuitry. ESP32 with two 32-bit, LX6 CPU, clocked at up to 240MHz, using 7-level pipeline architecture. ESP32 also integrates a wealth of analog sensing and digital interface.
ESP32’s ultra-low-power RF architecture and patented power-saving technology extend the battery life of practical applications.
ESP32 fully complies with WiFi 802.11b / g / n / e / i and Bluetooth 4.2 standards, integrated WiFi / Bluetooth / BLE RF and low power technology, and supports open real-time operating system RTOS. ESP32’s integrated tuning cache helps improve system performance and optimize system storage. The flexible RAM / ROM partition architecture allows users to customize to meet specific requirements and usage.
ESP32 can be used as a standalone application or as a slave for a host MCU. As a slave, the ESP32 provides WiFi and Bluetooth via the SPI / SDIO or I2C / UART interface.
2.1 WiFi.1 WiFi
• 802.11 b / g / n / e / i
• 802.11 n (2.4 GHz) at speeds up to 150 Mbps
• 802.11 e: QoS mechanism to implement wireless multimedia technology
• A-MPDU and A-MSDU frame aggregation techniques
• Block reply
• Fragmentation and reorganization
• Beacon automatic monitoring / scanning
• 802.11 i security features: pre-authentication and TSN
• Supports WPA / WPA2 / WPA2-Enterprise / WPS encryption
• Infrastructure BSS Station mode / SoftAP mode
• Wi-Fi Direct (P2P), P2P discovery, P2P GO mode, and P2P power management
• UMA compatible and certified
• Antenna diversity and selection
2.2 Bluetooth 2 Bluetooth
• Bluetooth v4.2 complete standard, including traditional Bluetooth (BR / EDR) and low power Bluetooth (BLE)
• Supports standard Class-1, Class-2 and Class-3, and eliminates the need for external power amplifiers
• Enhanced precision power control
• Output power up to + 10 dBm
• The NZIF receiver has BLE receive sensitivity of -98 dBm
• Adaptive Frequency Hopping (AFH)
• Standard HCI based on SDIO / SPI / UART interface
• High-speed UART HCI with speeds up to 4 Mbps
• Supports BT 4.2 controller and host protocol stack
• Service Discovery Protocol (SDP)
• Universal Access Application (GAP)
• Security Management Protocol (SMP)
• Low power Bluetooth
• Supports all GATT-based low-power Bluetooth applications
• SPP-Like Low Power Bluetooth Data Transparency Protocol
• BLE Beacon
• CVSD and SBC audio codec algorithms
• Bluetooth piconet and Scatternet
2.3 CPU and storage
• Xtensa® 32-bit LX6 dual-core processor with computing power up to 600 DMIPS
• 448 KByte ROM
• 520 KByte SRAM
• 16 KByte SRAM in RTC
• The QSPI can connect up to four Flash / SRAMs, each with 16 MBytes of Flash
• Supply voltage: 2.2V to 3.6V
2.4 clock and timer
Built-in 8 MHz oscillator for self-calibration
• Built-in RC oscillator for self-calibration
• Supports external 2 MHz to 40 MHz crystal
• Supports external 32 kHz crystal for RTC, supports self-calibration
• 2 timer groups each consisting of 2 64-bit general-purpose timers and 1 master system watchdog
• RTC timers with sub-second precision
• RTC watchdog
2.5 Peripheral interface
• 12-bit SAR ADC with up to 18 channels
• 2 8-bit D / A converters
• 10 touch sensors
• Temperature Sensor
• 4 SPIs
• 2 I2S
• 2 I2C
• 3 UARTs
• 1 Host SD / eMMC / SDIO
• 1 Slave SDIO / SPI
• Ethernet MAC interface with dedicated DMA to support IEEE 1588
• CAN 2.0
• IR (TX / RX)
• Motor PWM
• LED PWM, up to 16 channels
• Hall sensor
• Ultra-low power preamplifier
2.6 security mechanism .6 security mechanism
• Supports all IEEE 802.11 security features, including WFA, WPA / WPA2 and WAPI
• Safe start
• Flash encryption
• 1024-bit OTP, user-available up to 768 bits
• Encrypted hardware accelerator:
– HASH (SHA-2) library
– random number generator (RNG)
2.7 Application
• Universal low power IoT sensor hub
• Universal low power IoT recorder
• Video streaming of the camera
• OTT TV box / set-top box device
• music player
– Network music player
– Audio streaming media device
• Wi-Fi toys
– Counter
– toys anti-lost device
• Wi-Fi speech recognition device
• Headset
• Smart socket
• Home automation
• Mesh network
• Industrial wireless control
• Baby monitor
• Wearable electronic products
• Wi-Fi location-aware devices
• Security ID tag
• Healthcare
– Motion monitoring and anti-lost alarm
– Temperature recorder
ESP32 powered by a low-power Xtensa® LX6 32-bit dual-core processor with the following features:
4.1 CPU1 CPU
• 7-stage pipelined architecture that supports clock frequencies up to 240 MHz
• 16-bit / 24-bit instruction set improves code density
• Support for floating point units (FPU)
• Supports DSP instructions such as 32-bit amplifiers, 32-bit dividers and 40-bit accumulation multiplier (MAC)
• Supports 32 interrupt vectors from approximately 70 interrupt sources
The dual-core processor interface includes:
• Xtensa RAM / ROM instruction and data interface
• Xtensa local storage interface for quick access to external registers
• Interrupt with internal and external interrupt sources
• JTAG interface for debugging
4.2 on-chip storage on-chip storage
ESP32 on-chip storage includes:
• 448 KBytes of ROM for program startup and kernel function calls
• 520 KBytes on-chip SRAM for data and instruction storage
• 8 KBytes of SRAM in RTC, or RTC slow memory, can be accessed by coprocessor in Deep-sleep mode
• 8 kBytes of SRAM in RTC, RTC Fast Memory, which can be used for data storage and access by the primary CPU when RTC is started in Deep-sleep mode
• 1 kbit EFUSE, where 256 bits are system-specific (MAC address and chip set); the remaining 768 bits are reserved for user applications, including Flash encryption and chip ID
4.3 External Flash and SRAM
ESP32 supports up to four 16 MBytes of external QSPI Flash and static random access memory (SRAM) with AES-based hardware encryption to protect the developer’s programs and data.
ESP32 accesses external QSPI Flash and SRAM via cache:
• Up to 16 MBytes of external Flash maps to CPU code space, supports 8-bit, 16-bit and 32-bit access, and executable code.
• Up to 8 MBytes of external Flash and SRAM are mapped to CPU data space, supporting 8-bit, 16-bit and 32-bit access. Flash only supports read operations, SRAM can support read and write operations.

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